The present invention relates to a new and improved multiprocessor system.
Generally speaking, the multiprocessor system of the present development is of the type composed of a plurality of microprocessors or processors which are connected with a common collecting line serving for data transmission between the individual processors. Each processor or microprocessor is connected by means of a bus composed of address lines, data lines and control lines, with at least one respective read-only memory, read-write memory (RAM) and input-output components.
With such type multiprocessor systems each microprocessor or processor monitors the data transmission operations at the collecting line in consideration of data which is intended for such processor. The data transmitted by means of the collecting line or bus-bar contain, in each case, the addresses of those processors for which there is intended the related data. All microprocessors decode the addresses in order to determine the target processor. These state-of-the-art systems are afflicted with the drawback that they need a great deal of time for their operations, since all processors monitor the collecting line and the addresses must be decoded, and only the target processor is controlled. Additionally, this technique requires a relatively large expenditure in software.
In German Patent Publication No. 2,913,288 there has been taught to the art a multiprocessor system wherein these drawbacks are intended to be avoided. Between each processor and the collecting line there are arranged transmission or transfer devices structured such that the data exchange with the related processor only is accomplished during a predetermined repetitively occurring time interval. In this way the monitoring devices, instead of monitoring the related processors, monitor the collecting line in consideration of interruption requisitions or demands of other processors, so that in each instance there is only interrupted the course of the data processing of the addressed processor.
With the previously described multiprocessor system there can not be optimumly resolved certain data processing functions. If, for instance, there is to be accomplished a comparison of values determined according to the same criteria in the individual processors, then the comparison could be undertaken in each case between two processors, and the result is compared with the value of a further processor. It is possible to work in this fashion until there is determined the processor having, for instance, the smallest value. Depending upon the number of processors this technique requires a great deal of time and there is needed an appreciable expenditure in software. Also, the data transfer by means of the line or bus-bar for other purposes during the comparison interval is markedly limited.